1. Field of the Invention
The present invention relates to control devices of disk array devices for storing data in a plurality of magnetic disk devices.
2. Description of the Related Art
In view of the fact that the input/output (I/O) performance or throughput of a disk subsystem (referred to as xe2x80x9csubsystemxe2x80x9d hereinafter) is less by approximately three to four orders of magnitude than the I/O throughput of main memories of computers with semiconductor memory devices as their storage media, attempts have conventionally been made to reduce this difference. Namely, attempts have been made to improve the I/O throughput of the subsystem. One prior known approach to improving the subsystem""s I/O throughput is to use a system, called xe2x80x9cdisk array,xe2x80x9d for constituting the subsystem from a plurality of magnetic disk devices such as fixed or xe2x80x9chardxe2x80x9d disk drives (HDD5) adaptable for use in storing data in such plurality of HDDs.
FIG. 2 shows an arrangement of one prior art disk array. This includes a plurality of channel interface (IF) units 11 for execution of data transmission between a host computer 50 and a disk array control device 2, a plurality of disk IF units 12 for execution of data transfer between HDDs 20 and the disk array control unit 2, a cache memory unit 14 for temporality storing data of HDDs 20, and a shared memory unit 15 for storing control information as to the disk array controller 2 (for example, information concerning data transfer control between the channel and disk IF units 11, 12 and the cache memory unit 14), wherein the cache memory unit 14 and shared memory unit 15 are arranged so that these are accessible from all of the channel IF units 11 and disk IF units 12. With this disk array, the channel and disk IF units 11 and disk IF units 12 are connected to the shared memory unit 15 on a one-to-one basis; similarly, the channel IF units 11 and disk IF units 12 are connected one by one to the cache memory unit 14. This connection form is called the star connection.
The channel IF unit 11 has an interface for connection with the host computer 50 and also a microprocessor (not shown) for controlling input/output with respect to the host computer 50. The disk IF unit 12 has an interface for connection to the HDDs 20 and a microprocessor (not shown) for controlling input/output relative to HDDs 20. The disk IF units 12 also executes RAID functions.
FIG. 3 shows a configuration of another prior art disk array. It includes a plurality of channel IF units 11 for execution of data transfer between a host computer 50 and a disk array controller 3, a plurality of disk IF units 12 for execution of data transfer between HDDs 20 and the disk array controller 3, a cache memory unit 14 for temporality storing data of HDDs 20, and a shared memory unit 15 for storing control information as to the disk array controller 3 (e.g. information concerning data transfer control between the channel and disk IF units 11, 12 and the cache memory unit 14), wherein each of channel IF units 11 and disk IF units 12 is connected by a shared bus 130 to the shared memory unit 15 whereas each channel and disk IF unit 11, 12 is connected by a shared bus 131 to the cache memory unit 14. Such connection form is called the shared bus connection.
To render scalable the disk array""s architectures, it is required that the disk IF units be additionally provided in accordance with the required number of disks being connected to the disk control device while increasingly providing the channel IF units within the disk array controller as per the required number of channels associated with a host computer(s). However, with the disk array controller of the shared bus connection form shown in FIG. 3, because it is impossible to change or modify the transfer ability of the once-mounted shared bus in accordance with the add-in provision of the channel IF units and disk IF units, it remains difficult to flexibly accommodate such add-in extended reconfiguration of the channel IF units and disk IF units.
With the shared bus connection form shown in FIG. 3, in the case of employing high-performance processors as the microprocessors provided in the channel IF units and those in the disk IF units, the shared bus""s transfer ability becomes a bottle neck when compared to the performance of these processors, which leads to difficulty in keeping up with the growth of high-speed computer processor technology.
Further, in the shared bus connection form shown in FIG. 3, in cases where disturbance or operation failures occur at any one of the plurality of channel IF units (or a plurality of disk IF units) as connected to the shared bus, it is difficult to specify which one of the channel IF units (or, disk IF units) suffers from such trouble.
On the contrary, in the disk array controller of the star connection form shown in FIG. 2, it is possible to increase the internal path performance or throughput in a way proportional to the number of access paths being connected to either the shared memory unit or cache memory unit, which in turn makes it possible to increase the throughput of internal paths in accordance with the add-in reconfiguration of the channel and disk IF units or alternatively with the performance of processors used. In addition, as the one-to-one (star) connection is used between the channel IF and disk IF units and the cache memory unit or between the channel and disk IF units and the shared memory unit, it is easy to specify a channel IF unit (or disk IF unit) at which an operation failure was occurred.
In the disk array controller of the star connection form, increasing the number of those channel IF units or disk IF units as built therein would result in an increase in number of access paths between the channel and disk IF units and the cache memory unit and between the channel and disk IF units and the shared memory unit. Additionally, the throughput called for disk array control devices tends to further increase due to employment of high-speed channels, such as fiber channel, for connection between host computers and disk array controllers; in order to satisfy this need for improvement of throughput, it should be required to increase the number of access paths between the channel and disk IF units and the cache memory unit and between the former and the shared memory unit to thereby improve the internal path throughput.
However, the data amount of a single data segment or datum to be stored in the cache memory is much greater than the data amount of a single control information item being stored in the shared memory. One example is that in a disk control device as connected to a mainframe, a single datum being stored in the cache memory is several kilobytes (KB) or more or less (for example, 2 KB) whereas one control information item stored in the shared memory is several bytes or therearound (e.g. 4 bytes). Another example is that in disk control devices as connected to host computers of open architectures, a single datum as stored in the cache memory is several tens of byte (e.g. 64 bytes) whereas a single control information item stored in the shared memory is about several bytes (e.g. 4 bytes). Accordingly, the amount of data to be transferred between the channel and disk IF units and the cache memory unit is extremely greater than the data mount being transferred between the channel and disk IF units and the shared memory unit, which leads to a need for letting the data width of an access path between the channel and disk IF units and the cache memory unit be wider than the data width of an access path between the channel and disk IF units and the shared memory unit. For instance, the access path of the former is constituted from a 16-bit width bus whereas the latter is from a 4-bit width bus. For this reason, increasing the line number of access paths between the channel and disk IF units and the cache memory unit would result in creation of a problem of shortage of the pin number of an LSI(s) of the cache memory unit for connection of the access paths thereof. Additionally, in order to shorten the response time to the host computer of a disk array control device, it is also required to minimize a time taken to give access to the control information as stored in the shared memory unit.
It is therefore an object of the present invention to provide a disk array control device having high throughput and short response time which takes into consideration characteristics of data to be stored in a cache memory and shared memory and of access characteristics to these memories, along with a subsystem using the same.
It is another an object of the invention is to provide a disk array control device with access paths having high throughput between channel IF units and disk IF units and a cache memory unit and also with access paths having high throughput between such channel and disk IF units and a shared memory and with a short access time, and also a subsystem using the disk array controller.
To attain the foregoing objects, a disk array control device is provided which includes a plurality of channel interface units having an interface with a host computer, a plurality of disk interface units having an interface with a magnetic disk device, a cache memory unit for temporarily storing therein data being read/written with respect to said magnetic disk device, and a shared memory unit for storage of control information as to data transmission between the channel interface units and disk interface units and said cache memory unit, wherein each channel interface unit executes data transfer between the interface with the host computer and the cache memory unit whereas each disk interface unit executes data transfer between the interface with the magnetic disk device and the cache memory unit, characterized in that the connection form between said plurality of channel interface units and said plurality of disk interface units and said cache memory unit is different from the connection form between said plurality of channel interface units and said plurality of disk interface units and said shared memory unit.
Preferably, the plurality of channel interface units and said plurality of disk interface units are connected via a selector unit to said cache memory unit, while said plurality of channel interlace units and said plurality of disk interface units are directly connected via no selector unit to said shared memory unit respectively.
Also preferably, the plurality of channel interface units and said plurality of disk interface units are connected via one or more selector units to the cache memory unit, and the plurality of channel interface units and the plurality of disk interface units as well as said shared memory unit are connected to a common bus.
Also preferably, the plurality of channel interface units and said plurality of disk interface units are connected to said cache memory unit via an interconnection network using one or more switches whereas said plurality of channel interface units and said plurality of disk interface units are directly connected to said shared memory unit respectively.
These and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.